1. Technical Field
The invention relates generally to semiconductor memory fabrication, and more particularly, to a deep trench capacitor through a silicon-on-insulator (SOI) substrate and methods of forming the same.
2. Background Art
Static random access memory (SRAM) is used in microprocessors built on semiconductor-on-insulator (SOI) substrates for cache memory. SOI substrates include a silicon layer on a buried insulator layer, such as a buried silicon oxide (BOX), on a silicon substrate. Embedded dynamic random access memory (eDRAM), however, is also advantageous for SOI substrates because an eDRAM cell uses approximately a fifth of the space of an SRAM cell. For example, an SRAM typically uses six transistors arranged in planar manner, while an eDRAM uses one transistor and a deep trench capacitor extending into the silicon substrate. Accordingly, eDRAM could be used to drastically reduce chip size. Alternatively, eDRAM may be used to provide up to approximately five times more memory capacity in the same amount of space.
One challenge in employing eDRAM in SOI substrate is the amount of lateral undercut into the BOX layer of the SOI substrate that occurs during the deep trench creation process. For example, in a typical eDRAM cell layout, trench-to-trench spacing is usually minimized or close to a minimum spacing. If the BOX layer undercut is large, deep trenches may actually short one another as the undercut may be filled with conductor, e.g., doped N+ polysilicon. In particular, current technology employs two hydrofluoric (HF) acid etches: one to remove a hardmask used to open the trenches, and a second to remove arsenic-doped glass (ASG) and its capping layer, e.g., tetraethyl orthosilicate, Si(OC2H5)4 (TEOS). The ASG is used to form a buried electrode of the eDRAM by out-diffusing the arsenic into surrounding silicon, and then removing the ASG. Unfortunately, these two HF acid etches completely remove the BOX layer between deep trenches in 90 nm technology.
One approach to addressing this situation is to provide a deeper active area etch that etches silicon throughout the entire BOX layer thickness. Unfortunately, under this approach, the shallow trench isolation (STI) fill (used to electrically isolated devices on the substrate) and planarization process would need to be modified from standard practices. In particular, because the active area troughs are deeper in the eDRAM array, a thicker silicon oxide would be needed to fill the deeper STI in the eDRAM array. If the active area etch is highly selective to silicon oxide, as is common, this would result in only the silicon of the SOI substrate being etched away while the BOX layer remains relatively unperturbed in the non-eDRAM areas (e.g., logic and SRAM areas). Unfortunately, this approach creates a situation where more silicon oxide would need to be polished from the non-eDRAM areas than the eDRAM array. As a result, the planarization process would have to be adjusted to account for the greater topography.
A solution to minimize the BOX layer undercut as much as possible to allow for an easy integration path for trench e-DRAM in SOI substrates is needed.